1. Field of the Invention:
The present invention relates to a semiconductor device and a method for manufacturing the same. The present invention relates particularly to a semiconductor device having conductive layers formed by plating processing, and a method for manufacturing the same.
This application is a counterpart of Japanese patent application, Serial Number 204616/2003, filed Jul. 30, 2003.
2. Description of the Related Art:
With size reductions in portable devices, there has been a demand for a reduction in the size of semiconductor devices mounted in the portable devices. In order to meet such a demand, a semiconductor device called a “Chip Size Package” having outside dimensions approximately identical to those of a semiconductor chip has come along. As one form of the chip size package, there is known a semiconductor device called a “Wafer Level Chip Size Package” or “Wafer Level Chip Scale Package”. In such a wafer level chip size package (hereinafter called “WCSP”), a resin sealing process step for protecting circuit elements from external environments, and an external terminal forming process step are collectively executed in a wafer state prior to wafer fractionalization.
One characteristic of the above WCSP resides in that the WCSP includes redistribution wirings and post electrodes (also called “columnar electrodes and protruded electrodes”). The redistribution wirings are used to arrange external terminals in area form. The post electrodes are used to relax stress caused by the difference between a thermal expansion coefficient of a semiconductor substrate and a thermal expansion coefficient of a printed circuit board. The redistribution wirings and the post electrodes are both formed by plating processing.
As a plating solution for forming the redistribution wirings and the post electrodes, the same one is generally used. A plating processing condition for forming the redistribution wirings and a plating processing condition for forming the post electrodes are generally set to the same.
The WCSP having the redistribution wirings and post electrodes formed by plating processing has been described in, for example, the following document (see, for example, a patent document 1).
Patent document 1
Japanese Laid-open Patent Application No. 2003-60120 (see FIGS. 3 and 4)
However, the WCSP needs post electrodes each having a relatively high height (height ranging from approximately 90 to 150 micrometers (μm)) for the purpose of stress relaxation. Thus, a long plating processing time interval required to form each of the post electrodes is not negligible in terms of a productivity improvement of WCSP.
It is also considered that in order to shorten the plating processing time interval, a plating processing condition at the formation of redistribution wirings and post electrodes is changed to such a condition that the time required to precipitate a plated layer becomes short. However, it turned out that when the plating condition changed simply, a phenomenon called “burning” would occur in the precipitated plated layer or abnormal precipitation would occur therein. Further, it also turned out that variations in the thickness of a plated layer in a wafer plane would increase materially.
Since the redistribution wiring is particularly micro-fabricated in its wiring width and thickness as compared with the post electrode, a current that flows through the redistribution wiring might change from a design value when the above phenomenon occurs. It is undesirable to cause such a case.
Thus, it has been desired to provide a semiconductor device capable of improving its productivity while maintaining electrical characteristics thereof, and a manufacturing method thereof.